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Texas Instruments /CC13x0 /GPT2 /TBMATCHR

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Interpret as TBMATCHR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBMATCHR

Description

Timer B Match Register

When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases.

Note : This register is updated internally (takes effect) based on TBMR.TBMRSU

Fields

TBMATCHR

TBMATCHR

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data